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| PRELIMINARY Integrated Circuit Systems, Inc. ICS8530I-01 LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER FEATURES * (16) differential 3.3V LVPECL outputs * CLK, nCLK input pair * CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL * Maximum output frequency: 500MHz * Translates any single-ended input signal to 3.3V LVPECL levels with a resistor bias on nCLK input * Output skew: 50ps (typical) * Part-to-part skew: 100ps (typical) * Additive phase jitter, RMS @ 106.25MHz: 0.022ps (typical) @ 25C * 3.3V output operating supply * -40C to 85C ambient operating temperature GENERAL DESCRIPTION The ICS8530I-01 is a low skew, 1-to-16 Differential-to-3.3V LVPECL Fanout Buffer and a memHiPerClockSTM ber of the HiPerClockSTM family of High Performance Clock Solutions from ICS. The CLK, nCLK pair can accept most standard differential input levels. The high gain differential amplifier accepts peak-topeak input voltages as small as 150mV as long as the common mode voltage is within the specified minimum and maximum range. ICS Guaranteed output and part-to-part skew characteristics make the ICS8530I-01 ideal for those clock distribution applications demanding well defined performance and repeatability. BLOCK DIAGRAM CLK nCLK PIN ASSIGNMENT nCLK VCCO Q15 nQ15 Q14 nQ14 VEE Q13 nQ13 Q12 nQ12 VCCO 48 47 46 45 44 43 42 41 40 39 38 37 1 36 2 35 3 34 4 33 5 32 6 31 7 30 8 29 9 28 10 27 11 26 12 25 13 14 15 16 17 18 19 20 21 22 23 24 Q0 nQ0 Q1 nQ1 Q2 nQ2 Q3 nQ3 Q4 nQ4 Q5 nQ5 Q6 nQ6 Q7 nQ7 Q15 nQ15 Q14 nQ14 Q13 nQ13 Q12 nQ12 Q11 nQ11 Q10 nQ10 Q9 nQ9 Q8 nQ8 VCCO Q11 nQ11 Q10 nQ10 VEE Q9 nQ9 Q8 nQ8 VCCO VCC ICS8530I-01 CLK VCCO nQ0 Q0 nQ1 Q1 VEE nQ2 Q2 nQ3 Q3 Vcco 48-Lead TQFP, E-Pad 7mm x 7mm x 1.0mm body package Y Package Top View The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 8530DYI-01 www.icst.com/products/hiperclocks.html REV. A FEBRUARY 25, 2005 1 VCCO nQ4 Q4 nQ5 Q5 VEE nQ6 Q6 nQ7 Q7 VCCO VCC PRELIMINARY Integrated Circuit Systems, Inc. ICS8530I-01 LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER Type Power Output Output Power Output Output Power Output Output Output Output Output Output Description Output supply pins. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Negative supply pins. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Core supply pins. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels.. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. TABLE 1. PIN DESCRIPTIONS Number 1, 11, 14, 24, 25, 35, 38, 48 2, 3 4, 5 6, 19, 30, 43 7, 8 9, 10 12, 13 15, 16 17, 18 20, 21 22, 23 26, 27 28, 29 36 37 39, 40 41, 42 44, 45 46, 47 NOTE: Pullup and Name VCCO Q11, nQ11 Q10, nQ10 V EE Q9, nQ9 Q8, nQ8 VCC Q7, nQ7 Q6, nQ6 Q5, nQ5 Q4, nQ4 Q3, nQ3 Q2, nQ2 CLK Input Pulldown Non-inver ting differential clock input. nCLK Input Pullup Inver ting differential clock input. Q15, nQ15 Output Differential output pair. LVPECL interface levels. Q14, nQ14 Output Differential output pair. LVPECL interface levels. Q13, nQ13 Output Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Q12, nQ12 Output Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF k k TABLE 3. FUNCTION TABLE Inputs CLK 0 1 0 1 Biased; NOTE 1 Biased; NOTE 1 nCLK 1 0 Biased; NOTE 1 Biased; NOTE 1 0 1 Q0:Q15 LOW HIGH LOW HIGH HIGH LOW Outputs nQ0:nQ15 HIGH LOW HIGH LOW LOW HIGH Input to Output Mode Differential to Differential Differential to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Polarity Non Inver ting Non Inver ting Non Inver ting Non Inver ting Inver ting Inver ting NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels". 8530DYI-01 www.icst.com/products/hiperclocks.html 2 REV. A FEBRUARY 25, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS8530I-01 LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER 4.6V -0.5V to VCC + 0.5V 50mA 100mA 27.6C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCO = 3.3V5%, TA = -40C TO 85C Symbol VCC VCCO I EE Parameter Core Supply Voltage Output Supply Voltage Power Supply Current Test Conditions Minimum 3.135 3.135 Typical 3.3 3.3 115 Maximum 3.465 3.465 Units V V mA TABLE 4B. DIFFERENTIAL DC CHARACTERISTICS, VCC = VCCO = 3.3V5%, TA = -40C TO 85C Symbol IIH IIL VPP Parameter Input High Current Input Low Current CLK nCLK CLK nCLK Test Conditions VCC = VIN = 3.465V VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V VCC = 3.465V, VIN = 0V -5 -150 1.3 VCC - 0.85 Minimum Typical Maximum 150 5 Units A A A A V V Peak-to-Peak Input Voltage 0.15 Common Mode Input Voltage; VCMR VEE + 0.5 NOTE 1, 2 NOTE 1: For single ended applications, the maximum input voltage for CLK, nCLK is VCC + 0.3V. NOTE 2: Common mode voltage is defined as VIH. TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = VCCO = 3.3V5%, TA = -40C TO 85C Symbol VOH VOL VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing Test Conditions Minimum VCCO - 1.4 VCCO - 2.0 0.6 Typical Maximum VCCO - 0.9 VCCO - 1.7 1.0 Units V V V NOTE 1: Outputs terminated with 50 to VCCO-2V. 8530DYI-01 www.icst.com/products/hiperclocks.html 3 REV. A FEBRUARY 25, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS8530I-01 LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER Test Conditions Minimum Typical 1.35 50 100 106.25MHz, 25C Integration Range: 12KHz to 20MHz 106.25MHz, 85C Integration Range: 12KHz to 20MHz 212.5MHz, 25C Integration Range: 12KHz to 20MHz 212.5MHz, 85C Integration Range: 12KHz to 20MHz 20% to 80% @ 50MHz 20% to 80% @ 50MHz 0.022 0.026 0.033 0.034 300 300 700 700 Maximum 500 Units MHz ns ps ps ps ps ps ps ps ps % TABLE 5. AC CHARACTERISTICS, VCC = VCCO = 3.3V5%, TA = -40C TO 85C Symbol fMAX tPD Parameter Output Frequency Propagation Delay; NOTE 1 Output Skew; NOTE 2, 4 Par t-to-Par t Skew; NOTE 3, 4 tsk(o) tsk(pp) tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section tR tF Output Rise Time Output Fall Time odc Output Duty Cycle 50 All parameters measured at 250MHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. 8530DYI-01 www.icst.com/products/hiperclocks.html 4 REV. A FEBRUARY 25, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS8530I-01 LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER ADDITIVE PHASE JITTER The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in 0 -10 -20 -30 -40 -50 -60 the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. Additive Phase Jitter @ 106.25MHz, 25C (12KHz to 20MHz) = 0.022ps typical SSB PHASE NOISE dBc/HZ -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k 1M 10M 100M OFFSET FROM CARRIER FREQUENCY (HZ) As with most timing specifications, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The de- vice meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment. 8530DYI-01 www.icst.com/products/hiperclocks.html 5 REV. A FEBRUARY 25, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS8530I-01 LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER ADDITIVE PHASE JITTER The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in 0 -10 -20 -30 -40 -50 -60 the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. Additive Phase Jitter @ 106.25MHz, 85C (12KHz to 20MHz) = 0.026ps typical SSB PHASE NOISE dBc/HZ -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k 1M 10M 100M OFFSET FROM CARRIER FREQUENCY (HZ) As with most timing specifications, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The de- vice meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment. 8530DYI-01 www.icst.com/products/hiperclocks.html 6 REV. A FEBRUARY 25, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS8530I-01 LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER ADDITIVE PHASE JITTER The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in 0 -10 -20 -30 -40 -50 -60 the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. Additive Phase Jitter @ 212.5MHz, 25C (12KHz to 20MHz) = 0.033ps typical SSB PHASE NOISE dBc/HZ -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k 1M 10M 100M OFFSET FROM CARRIER FREQUENCY (HZ) As with most timing specifications, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The de- vice meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment. 8530DYI-01 www.icst.com/products/hiperclocks.html 7 REV. A FEBRUARY 25, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS8530I-01 LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER ADDITIVE PHASE JITTER The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in 0 -10 -20 -30 -40 -50 -60 the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. Additive Phase Jitter @ 212.5MHz, 85C (12KHz to 20MHz) = 0.034ps typical SSB PHASE NOISE dBc/HZ -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k 1M 10M 100M OFFSET FROM CARRIER FREQUENCY (HZ) As with most timing specifications, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The de- vice meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment. 8530DYI-01 www.icst.com/products/hiperclocks.html 8 REV. A FEBRUARY 25, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS8530I-01 LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION 2V V CC V CC, VCCO Qx SCOPE nCLK V PP LVPECL nQx Cross Points V CMR CLK VEE VEE -1.3V 0.165V 3.3V OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL nQx Qx nQy Qy PART 1 nQx Qx PART 2 nQy Qy tsk(o) tsk(pp) OUTPUT SKEW nCLK PART-TO-PART SKEW 80% CLK nQ0:nQ15 Q0:Q15 tPD 80% VSW I N G Clock Outputs 20% tR tF 20% PROPAGATION DELAY nQ0:nQ15 Q0:Q15 Pulse Width t PERIOD OUTPUT RISE/FALL TIME odc = t PW t PERIOD OUTPUT DUTY CYLE/PULSE WIDTH/PERIOD 8530DYI-01 www.icst.com/products/hiperclocks.html 9 REV. A FEBRUARY 25, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS8530I-01 LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VCC R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u R2 1K FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT TERMINATION FOR LVPECL OUTPUTS The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 2A and 2B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. 3.3V Zo = 50 125 125 FOUT FIN Zo = 50 Zo = 50 50 1 RTT = Z ((VOH + VOL) / (VCC - 2)) - 2 o 50 VCC - 2V RTT FOUT FIN Zo = 50 84 84 FIGURE 2A. LVPECL OUTPUT TERMINATION 8530DYI-01 FIGURE 2B. LVPECL OUTPUT TERMINATION REV. A FEBRUARY 25, 2005 www.icst.com/products/hiperclocks.html 10 PRELIMINARY Integrated Circuit Systems, Inc. ICS8530I-01 LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 3A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3E show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested 3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R2 50 R3 50 LVPECL Zo = 50 Ohm CLK nCLK HiPerClockS Input HiPerClockS Input R1 50 R2 50 FIGURE 3A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN ICS HIPERCLOCKS LVHSTL DRIVER BY FIGURE 3B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER BY 3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVPECL R1 84 R2 84 HiPerClockS Input R4 125 3.3V 3.3V Zo = 50 Ohm LVDS_Driv er CLK R1 100 nCLK Receiv er Zo = 50 Ohm FIGURE 3C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER BY FIGURE 3D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVDS DRIVER BY 3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 R3 125 R4 125 CLK Zo = 50 Ohm C2 nCLK HiPerClockS Input R5 100 - 200 R6 100 - 200 R1 84 R2 84 R5,R6 locate near the driver pin. FIGURE 3E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER WITH AC COUPLE 8530DYI-01 BY www.icst.com/products/hiperclocks.html 11 REV. A FEBRUARY 25, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS8530I-01 LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER solder as shown in Figure 4. For further information, please refer to the Application Note on Surface Mount Assembly of Amkor's Thermally /Electrically Enhance Leadframe Base Package, Amkor Technology. EXPOSED PAD THERMAL RELEASE PATH The expose metal pad provides heat transfer from the device to the P.C. board. The expose metal pad is ground pad connected to ground plane through thermal via. The exposed pad on the device to the exposed metal pad on the PCB is contacted through SOLDER M ASK SIGNAL TRACE SOLDER SIGNAL TRACE GROUND PLANE THERM AL VIA Expose Metal Pad (GROUND PAD) FIGURE 4. P.C. BOARD FOR EXPOSED PAD THERMAL RELEASE PATH EXAMPLE 8530DYI-01 www.icst.com/products/hiperclocks.html 12 REV. A FEBRUARY 25, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS8530I-01 LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS8530I-01. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8530I-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. * * Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 115mA = 398.5mW Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 16 * 30mW = 480mW Total Power_MAX (3.465V, with all outputs switching) = 398.5mW + 480mW = 878.5mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 22.6C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.879W * 22.6C/W = 104.9C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 6. THERMAL RESISTANCE JA FOR 48-PIN TQFP, E-PAD FORCED CONVECTION JA by Velocity (Linear Feet per Minute) 0 Multi-Layer PCB, JEDEC Standard Test Boards 27.6C/W 200 22.6C/W 500 20.7C/W 8530DYI-01 www.icst.com/products/hiperclocks.html 13 REV. A FEBRUARY 25, 2005 PRELIMINARY Integrated Circuit Systems, Inc. 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 5. ICS8530I-01 LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER VCCO Q1 VOUT RL 50 VCCO - 2V FIGURE 5. LVPECL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V. CCO * For logic high, VOUT = V (V CCO_MAX OH_MAX =V CCO_MAX - 0.9V -V OH_MAX ) = 0.9V =V - 1.7V * For logic low, VOUT = V (V CCO_MAX OL_MAX CCO_MAX -V OL_MAX ) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V - (V - 2V))/R ] * (V L OH_MAX CCO_MAX CCO_MAX -V OH_MAX ) = [(2V - (V CCO_MAX -V OH_MAX ))/R ] * (V L CCO_MAX -V OH_MAX )= [(2V - 0.9V)/50] * 0.9V = 19.8mW ))/R ] * (V L Pd_L = [(V OL_MAX - (V CCO_MAX - 2V))/R ] * (V L CCO_MAX -V OL_MAX ) = [(2V - (V CCO_MAX -V OL_MAX CCO_MAX -V OL_MAX )= [(2V - 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW 8530DYI-01 www.icst.com/products/hiperclocks.html 14 REV. A FEBRUARY 25, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS8530I-01 LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER RELIABILITY INFORMATION TABLE 7. JAVS. AIR FLOW TABLE FOR 48 LEAD TQFP, E-PAD JA by Velocity (Linear Feet per Minute) 0 200 22.6C/W 500 20.7C/W Multi-Layer PCB, JEDEC Standard Test Boards 27.6C/W TRANSISTOR COUNT The transistor count for ICS8530I-01 is: 930 8530DYI-01 www.icst.com/products/hiperclocks.html 15 REV. A FEBRUARY 25, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS8530I-01 LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER 48 LEAD TQFP, E-PAD PACKAGE OUTLINE - Y SUFFIX FOR -HD VERSION HEAT SLUG DOWN TABLE 8. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 e L ccc D3 & E 3 0.45 0 -2.00 --0.05 0.95 0.17 0.09 9.00 BASIC 7.00 BASIC 5.50 BASIC 9.00 BASIC 7.00 BASIC 5.50 BASIC 0.5 BASIC 0.60 0.75 7 0.08 7.00 ABC - HD MINIMUM NOMINAL 48 --1.00 0.22 1.20 0.15 1.05 0.27 0.20 MAXIMUM Reference Document: JEDEC Publication 95, MS-026 8530DYI-01 www.icst.com/products/hiperclocks.html 16 REV. A FEBRUARY 25, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS8530I-01 LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER Marking ICS8530DYI01 ICS8530DYI01 Package 48 Lead TQFP, E-Pad 48 Lead TQFP, E-Pad Shipping Packaging tray 1000 tape & reel Temperature -40C to 85C -40C to 85C TABLE 9. ORDERING INFORMATION Part/Order Number ICS8530DYI-01 ICS8530DYI-01T The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8530DYI-01 www.icst.com/products/hiperclocks.html 17 REV. A FEBRUARY 25, 2005 |
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